AN EFFICIENT AND SECURED RFID COMMUNICATION FOR MULTI PURPOSE APPLICATIONS
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GUDAPURI SUDHEER, MOHD.ABDUL SUMER, GADDE RAMA KRISHNA
ABSTRACT:Radio Frequency Identification (RFID) is an electronic tagging technology that allows objects to be automatically identified at a distance without a direct line-of- sight using an electromagnetic challenge-and-response exchange of data. An RFID system consists of RF readers and RF tags. RF tags are attached to objects, and used as a unique identifier of the objects. Due to the computational power constraints of passive tags, non-encryption-based singulation protocols have been recently developed, in which wireless jamming is used. However, the existing private tag access protocols without shared secrets rely on impractical physical layer assumptions, and thus they are difficult to deploy. To tackle this issue, we first redesign the architecture of RFID system by dividing an RF reader into two different devices, an RF activator and a trusted shield device (TSD). Then, we propose a novel coding scheme, namely Random Flipping Random Jamming (RFRJ), to protect tags’ content. Further, as an enhancement clock gating technique is implemented for memory organization schem for power reduction.
GUDAPURI SUDHEER, MOHD.ABDUL SUMER, GADDE RAMA KRISHNA
ABSTRACT:Radio Frequency Identification (RFID) is an electronic tagging technology that allows objects to be automatically identified at a distance without a direct line-of- sight using an electromagnetic challenge-and-response exchange of data. An RFID system consists of RF readers and RF tags. RF tags are attached to objects, and used as a unique identifier of the objects. Due to the computational power constraints of passive tags, non-encryption-based singulation protocols have been recently developed, in which wireless jamming is used. However, the existing private tag access protocols without shared secrets rely on impractical physical layer assumptions, and thus they are difficult to deploy. To tackle this issue, we first redesign the architecture of RFID system by dividing an RF reader into two different devices, an RF activator and a trusted shield device (TSD). Then, we propose a novel coding scheme, namely Random Flipping Random Jamming (RFRJ), to protect tags’ content. Further, as an enhancement clock gating technique is implemented for memory organization schem for power reduction.
HIGH SPEED FAULT TOLERANT ARCHITECTURE FOR MULTI LEVEL PHASE CHANGE MEMORY
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PALURI ANUSHA, R SANTHI SRI
ABSTRACT:The main objective of this project is to design a non-binary OLS code as applicable to multilevel a PCM. A PCM utilizes a multilevel scheme that permits to increase the storage density using ternary, quaternary and in the near future, octal cells. The resistance drift that occurs in a multilevel PCM due to the resistive characteristics of GST may cause errors in the stored information, thus degrading data integrity. The proposed codes utilize a non-binary scheme that is capable of correcting multi-symbol errors with a parallel decoder. Memory cells have been protected from soft errors for more than a decade; due to the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as well and must also be protected. A new approach to design fault-secure encoder and decoder circuitry for memory designs is introduced. The key novel contribution of this project is identifying and defining a new class of error-correcting codes whose redundancy makes the design of fault-secure detectors (FSD) particularly simple. OLS codes satisfies a new, restricted definition for ECCs which guarantees that the ECC codeword has an appropriate redundancy structure such that it can detect multiple errors occurring in both the stored codeword in memory and the surrounding circuitries. The parity-check Matrix of an FSD-ECC has a particular structure that the decoder circuit, generated from the parity-check Matrix, is Fault-Secure. Further this is enhanced with parallel corrector logic by combining both majority gate and row density blocks. Scalable encryption Algorithm is used as extension.
PALURI ANUSHA, R SANTHI SRI
ABSTRACT:The main objective of this project is to design a non-binary OLS code as applicable to multilevel a PCM. A PCM utilizes a multilevel scheme that permits to increase the storage density using ternary, quaternary and in the near future, octal cells. The resistance drift that occurs in a multilevel PCM due to the resistive characteristics of GST may cause errors in the stored information, thus degrading data integrity. The proposed codes utilize a non-binary scheme that is capable of correcting multi-symbol errors with a parallel decoder. Memory cells have been protected from soft errors for more than a decade; due to the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as well and must also be protected. A new approach to design fault-secure encoder and decoder circuitry for memory designs is introduced. The key novel contribution of this project is identifying and defining a new class of error-correcting codes whose redundancy makes the design of fault-secure detectors (FSD) particularly simple. OLS codes satisfies a new, restricted definition for ECCs which guarantees that the ECC codeword has an appropriate redundancy structure such that it can detect multiple errors occurring in both the stored codeword in memory and the surrounding circuitries. The parity-check Matrix of an FSD-ECC has a particular structure that the decoder circuit, generated from the parity-check Matrix, is Fault-Secure. Further this is enhanced with parallel corrector logic by combining both majority gate and row density blocks. Scalable encryption Algorithm is used as extension.
Implementation of a Low Power FIFO based BIST Process for CUT
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.B. KISHORE BABU,V. NAGA RANI
Abstract: The on line transparent test technique for detection of latent hard faults which develop in first input first output buffers of routers during field operation of NOC and also propose fault tolerant solution by introducing shared buffer in router. It provides alternative way in case of detection of faults otherwise used to improve efficiency. The technique involves repeating tests periodically to prevent accumulation of faults. NOC approach has emerged as a promising solution for on chip communications. The test technique utilized by the test hardware tries to incorporate the advantages of both parallel and serial approaches of testing embedded memories, thereby reducing the test time. For the test architecture proposed in the thesis, a test scheduling algorithm has been focusing on limiting the number of concurrent test blocks under power constraint with the aim of performing a power aware test of the memory cores. The scan chain reordering technique is the major criteria for the reduction of Power.
.B. KISHORE BABU,V. NAGA RANI
Abstract: The on line transparent test technique for detection of latent hard faults which develop in first input first output buffers of routers during field operation of NOC and also propose fault tolerant solution by introducing shared buffer in router. It provides alternative way in case of detection of faults otherwise used to improve efficiency. The technique involves repeating tests periodically to prevent accumulation of faults. NOC approach has emerged as a promising solution for on chip communications. The test technique utilized by the test hardware tries to incorporate the advantages of both parallel and serial approaches of testing embedded memories, thereby reducing the test time. For the test architecture proposed in the thesis, a test scheduling algorithm has been focusing on limiting the number of concurrent test blocks under power constraint with the aim of performing a power aware test of the memory cores. The scan chain reordering technique is the major criteria for the reduction of Power.
Implementation of Low Dense and Low Latency Discrete Cosine Transform
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P. KISHORE, M. GOPALA KRISHNA
Abstract: The main objective of this project is to design a recursive algorithm to obtain an orthogonal approximation of the DCT with half optimized complexity. This project presents a generalized recursive algorithm to obtain an orthogonal approximation of DCT where a pair of DCTs of length N/2 is used to derive approximate DCT of length N at the cost of N additions for input preprocessing. By using symmetries of basis vectors and perform recursive sparse matrix decomposition for deriving the proposed approximation algorithm. The proposed algorithm is highly scalable for hardware as well as software implementation of DCT of larger lengths, and they can be derived using the approximation of existing 8-point DCT to obtain approximate DCT of any power of two length, N>8. Further, this project is enhanced by using Vedic sutras. A technique of binary digits, decimal number multiplication is performed, and it is different from the conventional method of multiplication like Add and Shift. It presents a systematic methodology for high speed and area efficient Vedic Multiplier based on Vedic Mathematics. The multiplier architecture is based on the URDHVA – TIRYAGBYAM sutra of Ancient Indian Vedic Mathematics.
P. KISHORE, M. GOPALA KRISHNA
Abstract: The main objective of this project is to design a recursive algorithm to obtain an orthogonal approximation of the DCT with half optimized complexity. This project presents a generalized recursive algorithm to obtain an orthogonal approximation of DCT where a pair of DCTs of length N/2 is used to derive approximate DCT of length N at the cost of N additions for input preprocessing. By using symmetries of basis vectors and perform recursive sparse matrix decomposition for deriving the proposed approximation algorithm. The proposed algorithm is highly scalable for hardware as well as software implementation of DCT of larger lengths, and they can be derived using the approximation of existing 8-point DCT to obtain approximate DCT of any power of two length, N>8. Further, this project is enhanced by using Vedic sutras. A technique of binary digits, decimal number multiplication is performed, and it is different from the conventional method of multiplication like Add and Shift. It presents a systematic methodology for high speed and area efficient Vedic Multiplier based on Vedic Mathematics. The multiplier architecture is based on the URDHVA – TIRYAGBYAM sutra of Ancient Indian Vedic Mathematics.
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