POWER OPTIMIZED EFFICIENT FFMAC DESIGN FOR ELLIPTIC CURVE CRYPTOGRAPHY
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1. K.RAVI TEJA REDDY, 2. K.V.N.SWETHA
An efficient pipelined architecture can be made by using bit-parallel Finite Field (FF) Multiplier Accumulator (MAC) based on karatsuba-of man algorithm which is known for fast multiplication.
1. K.RAVI TEJA REDDY, 2. K.V.N.SWETHA
An efficient pipelined architecture can be made by using bit-parallel Finite Field (FF) Multiplier Accumulator (MAC) based on karatsuba-of man algorithm which is known for fast multiplication.
SECURED ADAPTIVE CONGESTION-AWARE ROUTING ALGORITHM FOR MESH NETWORK-ON-CHIP PLATFORM
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1. D.NAGARAJU, 2. K.V.N.SWETHA
Network-On-Chip (NoC) has surpassed the traditional bus based on-chip communication in offering better performance for data transfers among many processing, peripheral and other cores of high performance embedded systems. Adaptive routing provides an effective way of efficient on-chip communication among NoC cores.
1. D.NAGARAJU, 2. K.V.N.SWETHA
Network-On-Chip (NoC) has surpassed the traditional bus based on-chip communication in offering better performance for data transfers among many processing, peripheral and other cores of high performance embedded systems. Adaptive routing provides an effective way of efficient on-chip communication among NoC cores.
A FAST METHOD OF FOG AND HAZE REMOVAL
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1. KUNAPAREDDY .BHAVANA, 2. Dr.SHAIK UMAR FARUQ
Fog and Haze degrade the quality of preview and captured image by reducing the excellence and saturation
1. KUNAPAREDDY .BHAVANA, 2. Dr.SHAIK UMAR FARUQ
Fog and Haze degrade the quality of preview and captured image by reducing the excellence and saturation
ENERGY EFFICIENT FIN-FET BASED FULL ADDER EMPLOYING MULTIPLIER
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1. M.NANDINI MEDAPATI, 2. PULAKHANDAM VANI
In this paper, low PDP multiplier is proposed based on Full adder circuit. The full adder is designed using modified XOR/XNOR circuit. The proposed multiplier is designed using both conventional FETs and FinFETs.
1. M.NANDINI MEDAPATI, 2. PULAKHANDAM VANI
In this paper, low PDP multiplier is proposed based on Full adder circuit. The full adder is designed using modified XOR/XNOR circuit. The proposed multiplier is designed using both conventional FETs and FinFETs.
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