HIGH THROUGHPUT AND POWER OPTIMIZED AES CRYPTOGRAPHY SYSTEM USING SCAN CHAIN REORDERING
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SHAIK ASMA
This project plays vital role in all type of communication applications. This project designs a novel low-transition linear feedback shift register (LFSR) that is based on some new observations about the output sequence of a conventional LFSR. Security of a hardware implementation can be compromised by a random fault or a deliberate attack. The traditional testing methods are good at detecting random faults, but they do not provide to secure all type of attacks.
SHAIK ASMA
This project plays vital role in all type of communication applications. This project designs a novel low-transition linear feedback shift register (LFSR) that is based on some new observations about the output sequence of a conventional LFSR. Security of a hardware implementation can be compromised by a random fault or a deliberate attack. The traditional testing methods are good at detecting random faults, but they do not provide to secure all type of attacks.
UWB CPW FED FRACTAL PATCH ANTENNA WITH BANDNOTCHED FUNCTION EMPLOYING FOLDED T-SHAPED ELEMENT
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1 BODDAKAYALA NIKHITHA,2 K.V.GEETHIKA,3 C.CYNTHIA
An investigation of ultra-wide band coplanar waveguide fed antenna is presented consisting of a fractal radiating patch. The impedance match of the desired antenna is identified by the number of unit cells that are used in designing of the fractal patch by embedding the two rectangular patches in the ground plane.
1 BODDAKAYALA NIKHITHA,2 K.V.GEETHIKA,3 C.CYNTHIA
An investigation of ultra-wide band coplanar waveguide fed antenna is presented consisting of a fractal radiating patch. The impedance match of the desired antenna is identified by the number of unit cells that are used in designing of the fractal patch by embedding the two rectangular patches in the ground plane.
AREA EFFICIENT ALU DESIGN FOR LOW LATENCY APPLICATIONS USING RADIX-8 MODIFIED BOOTH ENCODING
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1. T.SATYA, 2.K.YAMINI
The main concept of this project is to design an efficient arithmetic logic unit. The reason behind choosing this topic as a research work is that, ALU is the key element of digital processors like as microprocessors, microcontrollers, central processing unit etc. Every digital domain based technology depends upon the operations performed by ALU either partially or whole. That’s why it highly required designing high speed ALU, which can enhance the efficiency of those modules which lies upon the operations performed by ALU.
1. T.SATYA, 2.K.YAMINI
The main concept of this project is to design an efficient arithmetic logic unit. The reason behind choosing this topic as a research work is that, ALU is the key element of digital processors like as microprocessors, microcontrollers, central processing unit etc. Every digital domain based technology depends upon the operations performed by ALU either partially or whole. That’s why it highly required designing high speed ALU, which can enhance the efficiency of those modules which lies upon the operations performed by ALU.
RELIABLE AND EFFICIENT POWER OPTIMIZED FFT PROCESSOR USING MODIFIED BOOTH ENCODING
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1. SYED SHEHNAZ, 2.SUDHAKARA RAO
The primary objective of this project is to design a multi-way FFT reversal switch that has the probability of processing the paired data stream. Fast Fourier Transform (FFT) has become ubiquitous in many engineering applications. Nowadays, FFT is most widely used block in many communication and signal processing systems. This project presents a new FFT pipeline processor for the FFT calculation of two independent data streams.
1. SYED SHEHNAZ, 2.SUDHAKARA RAO
The primary objective of this project is to design a multi-way FFT reversal switch that has the probability of processing the paired data stream. Fast Fourier Transform (FFT) has become ubiquitous in many engineering applications. Nowadays, FFT is most widely used block in many communication and signal processing systems. This project presents a new FFT pipeline processor for the FFT calculation of two independent data streams.
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