DATA ENCODING TECHNIQUES FOR REDUCING ENERGY CONSUMPTION IN NETWORK ON CHIP
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E.RAJESH., M.VARA PRASAD
ABSTRACT: This project focus on techniques aimed at reducing the power dissipated by the network links. In fact, the power dissipated by the network links is as relevant as that dissipated by routers and network interfaces (NIs) and their contribution is expected to increase as technology scales. In particular, this project present a set of data encoding schemes operating at flit level and on an end-to-end basis, which allows us to minimize both the switching activity and the coupling switching activity on links of the routing paths traversed by the packets. Further, this concept is enhanced by modifying majority gate with low complex structure. It yields less power consumption in whole encoder process.
E.RAJESH., M.VARA PRASAD
ABSTRACT: This project focus on techniques aimed at reducing the power dissipated by the network links. In fact, the power dissipated by the network links is as relevant as that dissipated by routers and network interfaces (NIs) and their contribution is expected to increase as technology scales. In particular, this project present a set of data encoding schemes operating at flit level and on an end-to-end basis, which allows us to minimize both the switching activity and the coupling switching activity on links of the routing paths traversed by the packets. Further, this concept is enhanced by modifying majority gate with low complex structure. It yields less power consumption in whole encoder process.
AN EFFICIENT DENOISING ARCHITECTURE FOR REDUCING OF IMPULSE NOISE IN IMAGES
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A.SUSWARA, T.VENU GOPAL
ABSTRACT:The main objective of this project is to design an efficient architecture for removal of random-valued impulse noise from captured image. The decision-tree-based detector to detect the noisy pixel and employs an effective design to locate the edge is proposed in this design. Decision-Tree-Based Impulse Detector is used as proposed methodology for this project. If there are noisy values, edges, or blocks in this region, the distribution of the values is different. Therefore, we determine whether current pixel is an isolation point by observing the smoothness of its surrounding pixels. The pixels with shadow suffering from noise have low similarity with the neighboring pixels and the so-called isolation point. The difference between it and its neighboring pixel value is large. Further, this project is enhanced using carry select adder in order to improve execution time. Here, serial adder is replaced with CSA to reduce computational time.
A.SUSWARA, T.VENU GOPAL
ABSTRACT:The main objective of this project is to design an efficient architecture for removal of random-valued impulse noise from captured image. The decision-tree-based detector to detect the noisy pixel and employs an effective design to locate the edge is proposed in this design. Decision-Tree-Based Impulse Detector is used as proposed methodology for this project. If there are noisy values, edges, or blocks in this region, the distribution of the values is different. Therefore, we determine whether current pixel is an isolation point by observing the smoothness of its surrounding pixels. The pixels with shadow suffering from noise have low similarity with the neighboring pixels and the so-called isolation point. The difference between it and its neighboring pixel value is large. Further, this project is enhanced using carry select adder in order to improve execution time. Here, serial adder is replaced with CSA to reduce computational time.
AREA DELAY POWER EFFICIENT FIXED POINT LMS ADAPTIVE FILTER WITH LOLAYW ADAPTATION
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S.NARESH BABU., M.VARA PRASAD
ABSTRACT:This project presents a novel partial product generator and proposes a strategy for optimized balanced pipelining across the time-consuming combinational blocks of the structure. To achieve lower adaptation-delay and area-delay-power efficient implementation proposed technique is adapted. In proposed method we use large processing elements (PEs) for achieving a lower adaptation delay with the critical path of one MAC operation. They have proposed a fine-grained pipelined design to limit the critical path to the maximum of one addition time, which supports high sampling frequency, but involves a lot of area overhead for pipelining and higher power consumption due to large number of pipeline latches. An efficient adder tree for pipelined inner-product computation is used to minimize the critical path and silicon area without increasing the number of adaptation delays.
S.NARESH BABU., M.VARA PRASAD
ABSTRACT:This project presents a novel partial product generator and proposes a strategy for optimized balanced pipelining across the time-consuming combinational blocks of the structure. To achieve lower adaptation-delay and area-delay-power efficient implementation proposed technique is adapted. In proposed method we use large processing elements (PEs) for achieving a lower adaptation delay with the critical path of one MAC operation. They have proposed a fine-grained pipelined design to limit the critical path to the maximum of one addition time, which supports high sampling frequency, but involves a lot of area overhead for pipelining and higher power consumption due to large number of pipeline latches. An efficient adder tree for pipelined inner-product computation is used to minimize the critical path and silicon area without increasing the number of adaptation delays.
BUILT IN GENERATION OF FUCNCTIONAL BROADSIDE TESTS USING A FIXED HARDWARE STRUCTURE
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MD.SADDAM, M.SHOBAN BABU
ABSTRACT:This project described an on-chip test generation method for functional broadside tests. The hardware was based on application of primary input sequences in order to allow the circuit to produce reachable states. Random primary input sequences were modeled to avoid repeated synchronization and thus yield varied sets of reachable states by implementing a decoder in between circuit and L.F.S.R. Two-pattern tests were obtained by using pairs of consecutive time units of the primary input sequences. The on-chip generation of functional broadside tests required simple hardware and achieved high fault coverage for testable circuits. Further, power can be reduced by using bit swapping LFSR. This technique yields less number of transitions for all pattern generation. Bit-swapping technique is less complex and more reliable to hardware miscommunications. C17,s27,ALU tests are performed in this concept.
MD.SADDAM, M.SHOBAN BABU
ABSTRACT:This project described an on-chip test generation method for functional broadside tests. The hardware was based on application of primary input sequences in order to allow the circuit to produce reachable states. Random primary input sequences were modeled to avoid repeated synchronization and thus yield varied sets of reachable states by implementing a decoder in between circuit and L.F.S.R. Two-pattern tests were obtained by using pairs of consecutive time units of the primary input sequences. The on-chip generation of functional broadside tests required simple hardware and achieved high fault coverage for testable circuits. Further, power can be reduced by using bit swapping LFSR. This technique yields less number of transitions for all pattern generation. Bit-swapping technique is less complex and more reliable to hardware miscommunications. C17,s27,ALU tests are performed in this concept.
LOW-POWER DIGITAL SIGNAL PROCESSOR ARCHITECTURE FOR WIRELESS SENSOR NODES
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M.NAGA RAJU, K.SRINIVASA RAO
ABSTRACT:The goal of this paper is to design low power WSN digital processor using parallel prefix technique. Wireless data acquisition, storing, performing arithmetic operations are three main key steps involved in this project. In this project, design and implementation of newly proposed folded tree architecture is presented for an efficient construction of DSP processors. Folded tree architecture has two phases. They are trunk and twig phase. Both phases are effectively utilized and designed in this project. This paper presents an overview of the key technologies required for low-energy distributed micro sensors. These include power aware computation/communication component technology, low-energy signalling and networking, system partitioning considering computation and communication trade-offs, and a power aware software infrastructure.
M.NAGA RAJU, K.SRINIVASA RAO
ABSTRACT:The goal of this paper is to design low power WSN digital processor using parallel prefix technique. Wireless data acquisition, storing, performing arithmetic operations are three main key steps involved in this project. In this project, design and implementation of newly proposed folded tree architecture is presented for an efficient construction of DSP processors. Folded tree architecture has two phases. They are trunk and twig phase. Both phases are effectively utilized and designed in this project. This paper presents an overview of the key technologies required for low-energy distributed micro sensors. These include power aware computation/communication component technology, low-energy signalling and networking, system partitioning considering computation and communication trade-offs, and a power aware software infrastructure.
HIGH SPEED AND ENERGY EFFICIENT CARRY SKIP ADDER OPERATING UNDER A WIDE RANGE OF SUPPLY VOLTAGE LEVELS
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M.JAYA KISHAN, M.SHOBAN BABU
ABSTRACT:This project presents a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrimination schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented.
M.JAYA KISHAN, M.SHOBAN BABU
ABSTRACT:This project presents a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrimination schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented.
Area–Delay–Power Efficient Carry-Select Adder
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M.V.KRISHNA., M.SHOBAN BABU
ABSTRACT:Carry Select Adder (CSLA) is one of the fastest adders use in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay.
M.V.KRISHNA., M.SHOBAN BABU
ABSTRACT:Carry Select Adder (CSLA) is one of the fastest adders use in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay.
Aging-Aware Reliable Multiplier Design with Adaptive Hold Logic
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L.SUDHEER., K.SRINIVASA RAO
ABSTRACT:In VLSI, scaling methods plays an important role in reducing the power dissipation from one technology node to other technology node. The two major constraints for delay in any VLSI circuits are latency and throughput. The negative bias temperature instability (NBTI) effect occurs when a pMOS transistor is under negative bias (Vgs= -VDD) increasing the threshold voltage of pMOS transistor and reducing the speed. A similar phenomenon, positive bias temperature instability (PBTI) effect occurs when an nMOS transistor is under positive bias. These both effects degrade the transistor speed and system may fail due to timing violations. In this paper, an Adaptive Hold Logic (AHL) circuit is proposed to mitigate the performance degradation due to aging effects. The main objective of this project is to design an aging-aware variable-latency multiplier with the AHL. This project proposes an aging-aware multiplier design with novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column bypassing multiplier and enhanced using Baugh-wooley multiplication.
L.SUDHEER., K.SRINIVASA RAO
ABSTRACT:In VLSI, scaling methods plays an important role in reducing the power dissipation from one technology node to other technology node. The two major constraints for delay in any VLSI circuits are latency and throughput. The negative bias temperature instability (NBTI) effect occurs when a pMOS transistor is under negative bias (Vgs= -VDD) increasing the threshold voltage of pMOS transistor and reducing the speed. A similar phenomenon, positive bias temperature instability (PBTI) effect occurs when an nMOS transistor is under positive bias. These both effects degrade the transistor speed and system may fail due to timing violations. In this paper, an Adaptive Hold Logic (AHL) circuit is proposed to mitigate the performance degradation due to aging effects. The main objective of this project is to design an aging-aware variable-latency multiplier with the AHL. This project proposes an aging-aware multiplier design with novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column bypassing multiplier and enhanced using Baugh-wooley multiplication.
A NEW TOOL FOR LIGHT WEIGHT ENCRYPTION ON ANDROID
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RAVITEJA., K.SRINIVASA RAO
ABSTRACT:The main objective of this project is to design a new tool for securing the information in Android Platform. This project based on light weight encryption scheme based on humming bird2. This used to secure the data by making use of password based authentication. The cryptographic key is derived from password based key generation method. Further this project can be extended to latency optimized processor for multipurpose applications. Along with time reduction, security also can be increased by using hybrid approaches in key generation processing. This light weight, latency optimization, more security is the vital key features of this designed crypto device.
RAVITEJA., K.SRINIVASA RAO
ABSTRACT:The main objective of this project is to design a new tool for securing the information in Android Platform. This project based on light weight encryption scheme based on humming bird2. This used to secure the data by making use of password based authentication. The cryptographic key is derived from password based key generation method. Further this project can be extended to latency optimized processor for multipurpose applications. Along with time reduction, security also can be increased by using hybrid approaches in key generation processing. This light weight, latency optimization, more security is the vital key features of this designed crypto device.
Embedded Transition Inversion Coding With Low Switching Activity for Serial Links
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S.PADMA, A.SWATHI
ABSTRACT:Here, in this project; embedded transition inversion (ETI) is proposed to reduce bit transitions in Serializing parallel buses. Implies power can be reduced further. This project proposes an embedded transition inversion (ETI) coding scheme that uses the phase difference between the clock and data in the transmitted serial data to tackle the problem of the extra indication bit. The technique is implemented in an optimized fashion using pipelining so that it can be used in practical systems with only a slight compromise in performance. This is achieved by calculating the decision as the data is being loaded on to the buffer and doing the encoding on the fly. This is one aspect which is lacking in most existing algorithms as they are not amenable to low delay implementation.
S.PADMA, A.SWATHI
ABSTRACT:Here, in this project; embedded transition inversion (ETI) is proposed to reduce bit transitions in Serializing parallel buses. Implies power can be reduced further. This project proposes an embedded transition inversion (ETI) coding scheme that uses the phase difference between the clock and data in the transmitted serial data to tackle the problem of the extra indication bit. The technique is implemented in an optimized fashion using pipelining so that it can be used in practical systems with only a slight compromise in performance. This is achieved by calculating the decision as the data is being loaded on to the buffer and doing the encoding on the fly. This is one aspect which is lacking in most existing algorithms as they are not amenable to low delay implementation.
SECURE AND EFFIEICENT LBIST FOR FEEDBACK SHIFT REGISTER BASED CRYPTOGRAPHIC SYSTEMS
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S.DIVYA, B.UMA MAHESWARI
ABSTRACT:The main motive of this project is to design a crypto device with low complexity and high security by using “ADVANCED AES” Algorithm along with BIST technique. The selective application of technological and related procedural safeguards is an important responsibility of every Federal organization in providing adequate security to its electronic data systems and coming to BIST concept there are two main functions that must be performed on-chip in order to implement built-in self-test (BIST): test pattern generation and output response analysis. The most common BIST schemes are based on pseudorandom test pattern generation using linear feedback shift registers (LFSR’S) and output response compaction using signature analyzers. To accomplish high security for a system we are using the crypto devices technique in our project. Further Scan chain reordering algorithm is implemented for crypto operations. Scan chain reordering provides, less power consumptions while doing operations.
S.DIVYA, B.UMA MAHESWARI
ABSTRACT:The main motive of this project is to design a crypto device with low complexity and high security by using “ADVANCED AES” Algorithm along with BIST technique. The selective application of technological and related procedural safeguards is an important responsibility of every Federal organization in providing adequate security to its electronic data systems and coming to BIST concept there are two main functions that must be performed on-chip in order to implement built-in self-test (BIST): test pattern generation and output response analysis. The most common BIST schemes are based on pseudorandom test pattern generation using linear feedback shift registers (LFSR’S) and output response compaction using signature analyzers. To accomplish high security for a system we are using the crypto devices technique in our project. Further Scan chain reordering algorithm is implemented for crypto operations. Scan chain reordering provides, less power consumptions while doing operations.
DESIGN AND IMPLEMENTATION OF FAST FLOTING POINT MULTIPLIER UNITS
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B.PRIYANKA, 2. B.UMA MAHESWARI
ABSTRACT:he main objective of this project is to design an efficient IEEE-754 floating point multiplier .This project focuses on double precision normalized binary floating point multiplication in IEEE754 format. The proposed design is compliant with IEEE-754 format and handles over flow, under flow, rounding and various exception conditions. FLOATING-POINT arithmetic provides a wide dynamic range, freeing special purpose processor designers from the scaling and overflow/underflow concerns that arise with fixed-point arithmetic. Further this project can be enhanced by replacing the general multiplier architecture with modified booth multiplication. This modification yields reduction of partial products to half. Partial products reduction changes system overall performance in an efficient manner.
B.PRIYANKA, 2. B.UMA MAHESWARI
ABSTRACT:he main objective of this project is to design an efficient IEEE-754 floating point multiplier .This project focuses on double precision normalized binary floating point multiplication in IEEE754 format. The proposed design is compliant with IEEE-754 format and handles over flow, under flow, rounding and various exception conditions. FLOATING-POINT arithmetic provides a wide dynamic range, freeing special purpose processor designers from the scaling and overflow/underflow concerns that arise with fixed-point arithmetic. Further this project can be enhanced by replacing the general multiplier architecture with modified booth multiplication. This modification yields reduction of partial products to half. Partial products reduction changes system overall performance in an efficient manner.
DESIGN AND ANALYSIS OF PROPELLER SHAFT USING VISCO ELASTIC DAMPING MATERIALS
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Gopi Enapanurthi, N. Charishma
ABSTRACT:Automotive drive Shaft is a very important components of vehicle. The overall objective of this paper is to design and analyze a composite drive shaft for power transmission. Substituting composite structures for conventional metallic structures has many advantages because of higher specific stiffness and strength of composite materials. In the present buckling analysis is performed to find out buckling factor. Model and harmonic analysis has done to find out natural frequency of shaft and resonance frequency of different materials. Impulse loading condition also taken into analysis to find out damping factor of particular materials.
Gopi Enapanurthi, N. Charishma
ABSTRACT:Automotive drive Shaft is a very important components of vehicle. The overall objective of this paper is to design and analyze a composite drive shaft for power transmission. Substituting composite structures for conventional metallic structures has many advantages because of higher specific stiffness and strength of composite materials. In the present buckling analysis is performed to find out buckling factor. Model and harmonic analysis has done to find out natural frequency of shaft and resonance frequency of different materials. Impulse loading condition also taken into analysis to find out damping factor of particular materials.
ANALYSIS OF MULTITHROW CRANK SHAFT
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D. Balaji, N. Charishma
Abstract: All the engine components are subjected to constant varying load which also varies in direction and due to these, components may fail. Bending and shear stress due to twisting are common stresses acting on crankshaft. Due to the repeated bending and twisting, crankshaft fails, as cracks form atfillets between thejournal and crank cheeks, and near the centre point journal. Hence, fatigue plays an important role in crankshaft development. Accurate prediction of fatigue life is very important to insure safety of components and its reliability. The main objective of this project is to modify the design to increase the fatigue life of four stroke diesel engine crankshaft. The drafting is done by using CREO 3.0 software, which is advanced modeling software for designing of simple to complex shapes. For the model developed, two types of analysis are performed, one is fatigue analysis and the other is modal analysis. Fatigue analysis is used to know the life and modal analysis for the natural frequencies of crankshaft before and after modification.
D. Balaji, N. Charishma
Abstract: All the engine components are subjected to constant varying load which also varies in direction and due to these, components may fail. Bending and shear stress due to twisting are common stresses acting on crankshaft. Due to the repeated bending and twisting, crankshaft fails, as cracks form atfillets between thejournal and crank cheeks, and near the centre point journal. Hence, fatigue plays an important role in crankshaft development. Accurate prediction of fatigue life is very important to insure safety of components and its reliability. The main objective of this project is to modify the design to increase the fatigue life of four stroke diesel engine crankshaft. The drafting is done by using CREO 3.0 software, which is advanced modeling software for designing of simple to complex shapes. For the model developed, two types of analysis are performed, one is fatigue analysis and the other is modal analysis. Fatigue analysis is used to know the life and modal analysis for the natural frequencies of crankshaft before and after modification.
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