PIPELINED ARCHITECTURE OF ELLIPTIC CURVE SCALAR MULTIPLICATION OVER GF (2M)
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1. KUNDURTHI HIMAJA, 2. K L SOWJANYA
An efficient pipelined architecture can be made by using bit-parallel Finite Field (FF) Multiplier Accumulator (MAC) based on karatsuba-of man algorithm which is known for fast multiplication.
1. KUNDURTHI HIMAJA, 2. K L SOWJANYA
An efficient pipelined architecture can be made by using bit-parallel Finite Field (FF) Multiplier Accumulator (MAC) based on karatsuba-of man algorithm which is known for fast multiplication.
ENERGY EFFICIENT RECONFIGURABLE APPLICATIONS USING CLOCK GATED AUTONOMOUS POWER GATING
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1. NALLA RATNA PRIYANKA, 2. TIKKIREDDI ADITYA KUMAR
This project introduces a set of techniques that, considering the dynamic streaming behavior of algorithms, can achieve power savings by selectively switching off parts of the circuits when they are temporarily inactive.
1. NALLA RATNA PRIYANKA, 2. TIKKIREDDI ADITYA KUMAR
This project introduces a set of techniques that, considering the dynamic streaming behavior of algorithms, can achieve power savings by selectively switching off parts of the circuits when they are temporarily inactive.
LATENCY OPTIMIZED FAULT TOLERANT ARCHITECTURE USING DMC AND MODIFIED CSA
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1. YARLAGADDA SUNITHA, 2. KAVULURU ANIL JAYAKIRAN
Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment.
1. YARLAGADDA SUNITHA, 2. KAVULURU ANIL JAYAKIRAN
Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment.
LOW POWER AND HIGHT THROUGHPUT CLOCK SPLITTING BASED ATPG FOR BIST
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1. ADDALA DURGA PRASAD, 2. S SAMBASIVA RAO DANNINA
The design for low power has become one of the greatest challenges in high-performance very large scale integration (VLSI) design.
1. ADDALA DURGA PRASAD, 2. S SAMBASIVA RAO DANNINA
The design for low power has become one of the greatest challenges in high-performance very large scale integration (VLSI) design.
RELIABLE AND ACCURATE LOW DENSE EFFICIENT MULTIPLIER
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1. TOGARU SRIDEVI, 2. V LALITHA SUVARNA
Consumption of Energy is the major factor, in the various processing application like DSP, ASIC, and FPGA. The motive of this work is to approximate the multiplication process.
1. TOGARU SRIDEVI, 2. V LALITHA SUVARNA
Consumption of Energy is the major factor, in the various processing application like DSP, ASIC, and FPGA. The motive of this work is to approximate the multiplication process.
AN IOT-AWARE ARCHITECTURE FOR COLLECTING AND MANAGING DATA RELATED ELECTRICITY DEPARTMENT
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1.T.SUMALATHA, 2. P.BABYSHAMILI
It is realized that one of the defective subsystems adding to the tremendous budgetary loss in Power Supply Company is the conventional metering and charging framework
1.T.SUMALATHA, 2. P.BABYSHAMILI
It is realized that one of the defective subsystems adding to the tremendous budgetary loss in Power Supply Company is the conventional metering and charging framework
INTERNET OF THINGS ENABLED REAL TIME WATER QUALITY AND WEATHER MONITORING SYSTEM
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1. M.NAGARAJU, 2. K. NARESH
In order to develop a new convenient online monitoring system for Internet of things, an online monitoring system based on cloud computing is designed.
1. M.NAGARAJU, 2. K. NARESH
In order to develop a new convenient online monitoring system for Internet of things, an online monitoring system based on cloud computing is designed.
IOT BASED ADVANCED WASTE MANAGEMENT SYSTEM FOR SMART CITY
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1. M. NARASIMHA RAO, 2. M.PURNA SEKHAR
In the recent decades, Urbanization has increased tremendously. At the same phase there is an increase in waste production.
1. M. NARASIMHA RAO, 2. M.PURNA SEKHAR
In the recent decades, Urbanization has increased tremendously. At the same phase there is an increase in waste production.
REAL-TIME DETECTION OF SIGNAL LIGHTS FOR DRIVING ASSISTANCE APPLICATIONS USING INTEGRATED APPROACH
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1. A. GOWTHAMI,2. M.VAMSI KRISHNA
For a Driving Assistance System, which is designed to improve safety on the roads, knowledge about the type of lane border markings and other painted road objects is required.
1. A. GOWTHAMI,2. M.VAMSI KRISHNA
For a Driving Assistance System, which is designed to improve safety on the roads, knowledge about the type of lane border markings and other painted road objects is required.
IOT BASED CYBER-PHYSICAL SYSTEM FOR THE AUTOMATION OF SHIPYARDS
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1.E. SUSMITHA,2. B.GANGADHAR RAO
The main objective of this concept is to monitor and track the ships by using integrated technology.
1.E. SUSMITHA,2. B.GANGADHAR RAO
The main objective of this concept is to monitor and track the ships by using integrated technology.
POWER OPTIMIZED MULTI BIT FLIPFLOP USING HIGH THROUGHPUT MODIFIED CLOCK GATING TECHNIQUE
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1. Y SUGANDHI NAIDU, 2.I RANI CHINNARI
This project introduces a set of techniques that, considering the dynamic streaming behavior of algorithms, can achieve power savings by selectively switching off parts of the circuits when they are temporarily inactive.
1. Y SUGANDHI NAIDU, 2.I RANI CHINNARI
This project introduces a set of techniques that, considering the dynamic streaming behavior of algorithms, can achieve power savings by selectively switching off parts of the circuits when they are temporarily inactive.
EXPERIMENTAL INVESTIGATION ON CI ENGINE USING TYRE PYROLYSIS OIL
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1. Ch Sai Krishna, 2N.Ranjith Kumar
Due to the scarcity of conventional fuels and the crude oil, the price was going up day to day and there will be no more conventional fuels in future and also increasing the environmental pollution by the usage of crude oils, there is a need for the search of alternative fuel sources for the automobile applications
1. Ch Sai Krishna, 2N.Ranjith Kumar
Due to the scarcity of conventional fuels and the crude oil, the price was going up day to day and there will be no more conventional fuels in future and also increasing the environmental pollution by the usage of crude oils, there is a need for the search of alternative fuel sources for the automobile applications
AREA EFFICIENT AND LOW LATENCY FINITE IMPULSE RESPONSE FILTER DESIGN
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1. GALAM KRISHNAIAH, 2.ALURI BULLI BABU
Filter is a frequency selective network. It passes a band of frequencies while attenuating the others.
1. GALAM KRISHNAIAH, 2.ALURI BULLI BABU
Filter is a frequency selective network. It passes a band of frequencies while attenuating the others.
EFFICIENT LATENCY AND POWER OPTIMIZED MODIFIED AES CRYPTOGRAPHY SYSTEM
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1.MD PARWEZ ALAM, 2.G SARITHA
This project plays vital role in all type of communication applications. This project designs a novel low-transition linear feedback shift register (LFSR) that is based on some new observations about the output sequence of a conventional LFSR.
1.MD PARWEZ ALAM, 2.G SARITHA
This project plays vital role in all type of communication applications. This project designs a novel low-transition linear feedback shift register (LFSR) that is based on some new observations about the output sequence of a conventional LFSR.
LOW POWER AND RECONFIGURABLE EFFICIENT FIR FILTERS WITH LOW LATENCY
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1 M.VENKATESWARLU 2. N. SANDEEP
Reconfigurable finite-impulse response (FIR) filters are one of the most widely implemented components in Internet of Things systems that require flexibility to support several target applications while consuming the minimum amount of power to comply with the strict design requirements of portable devices
1 M.VENKATESWARLU 2. N. SANDEEP
Reconfigurable finite-impulse response (FIR) filters are one of the most widely implemented components in Internet of Things systems that require flexibility to support several target applications while consuming the minimum amount of power to comply with the strict design requirements of portable devices
DESIGN OF HIGH PERFORMANCE FULL ADDER CIRCUIT USING GDI TRANSISTOR LOGIC
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1BANDAMNENI LAVANYA, 2R. SARANKUMAR
The current age of technology advancement it is necessary to design different new concepts to reduce area of the cell as well as power consumption. The adders are always meant to be the most fundamental requirements for process of high performance and other multi core devices.
1BANDAMNENI LAVANYA, 2R. SARANKUMAR
The current age of technology advancement it is necessary to design different new concepts to reduce area of the cell as well as power consumption. The adders are always meant to be the most fundamental requirements for process of high performance and other multi core devices.
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